Thermal Modeling and Management of Microprocessors

The most recent, and arguably one of the most difficult obstacles to the exponential growth in transistor density predicted by Moore’s Law is that of removing the large amount of heat generated within the tiny area of a microprocessor. The exponential increase in power density and its direct relation to on-chip temperature have, in recent processors, led to very high cooling costs. Since temperature also has an exponential effect on lifetime reliability and leakage power, it has become a first-class design constraint in microprocessor development akin to performance. This dissertation describes work to address the temperature challenge from the perspective of the architecture of the microprocessor. It proposes both the infrastructure to model the problem and several mechanisms that form part of the solution. This research describes HotSpot, an efficient and extensible microarchitectural thermal modeling tool that is used to guide the design and evaluation of various thermal management techniques. It presents several Dynamic Thermal Management (DTM) schemes that distribute heat both over time and space by controlling the level of computational activity. Processor temperature is not only a function of the power density but also the placement and adjacency of hot and cold functional blocks, determined by the floorplan of the microprocessor. Hence, this dissertation also explores various thermally mitigating placement choices available within a single core and across multiple cores of a microprocessor. It does so through the development of HotFloorplan, a thermally-aware microarchitectural floorplanner. Finally, through an analytical framework, this research also focuses on the spatial (size) granularity at which thermal management is important. If regions of very high power density are small enough, they do not cause hot spots. The granularity study quantifies this relationship and illustrates it using three different microarchitectural examples.